The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In semiconductor fabrication, features may be filled with conductive materials. For example, copper is used for back end of line (BEOL) interconnects. However, copper interconnects are challenging to fabricate in sub-10 nm technology nodes. Deposition of copper interconnects often involves first depositing a barrier layer to prevent inter-diffusion of elements from copper interconnects and substrate layers. However, a barrier material that maintains its integrity as its thickness is scaled below 2.5 nm has not been identified. As the linewidth scales to 10 nm (at the 5 nm technology node), the barrier will consume 5 nm of the linewidth and more than 50% of the line cross-section, increasing the resistance exponentially with each technology node beyond 10 nm. Additionally, copper has an electron mean free path of about 39 nm. As a result, in small critical dimension features, electrons hit the sidewalls resulting in a less elastic collision.